Optimizing power consumption in amplifiers

ABSTRACT

The present invention provides methods and apparatus for optimising power consumption in transistor amplifiers. The method comprises the step of adapting the amplifier characteristics of the transistor by adapting the bias impedance at the base of the transistor. The method may further comprise the step of adapting the amplifier characteristics of the transistor by adapting the quiescent collector current in the transistor.

The present invention relates to methods and apparatus for optimisingthe power consumption of amplifiers, whilst maintaining adequate signallinearity. In particular, the present invention relates to methods andapparatus for optimising power consumption of RF amplifiers for use inmobile telephone handsets, but may be applied to other types ofamplifier and other types of equipment, particularly battery poweredequipment.

Mobile telephone handsets are called upon to operate in severaldifferent modes, for example according to the availability of service,or the proximity of the assigned base station. For example, a hand setnear the edge of a cell may have to transmit at a relatively high powerin order for its signal to be received sufficiently clearly at the basestation. Conversely, it would be wasteful to have the handset operatingat high power when within close range of the base station. Mobiletelephone handsets may be called upon to operate according to a varietyof modes. For example, a CDMA mode requires quite strict linearity in RFamplification, while an AMPS mode is less sensitive to non-linearity.

Since a mobile telephone is powered by a portable battery, it isimportant to minimise power consumption in order to maximise the usefuloperating life of the handset between recharging of the battery. It isalso important to provide usable telephone service at as manygeographical locations as possible. When the handset is close to a basestation, only a relatively low transmission power is required to enablecommunication between the handset and the base station. When the handsetis further from the base station, or in a region of interference orlossy transmission path, a much higher transmission power is required,to provide communication. Of course, a mobile telephone handset could bearranged to transmit at full power at all times. However, this wouldresult in much reduced autonomy for the handset, requiring batteryCONFIRMATION COPY recharging at frequent intervals, and would introducean unacceptable level of noise into the transmission environment.

The present invention provides a method and apparatus for adjusting theoperating parameters of an amplifier, such as an RF amplifier for amobile telephone, to achieve an improved efficiency according to therequired mode of operation of the amplifier.

Accordingly, the present invention provides methods and apparatus asrecited in the appended claims.

The above, and further, objects, characteristics and advantages willbecome more clear with reference to the following description of certainembodiments thereof, in conjunction with the accompanying drawings,wherein

FIG. 1 shows a circuit diagram of a practical dual mode power amplifiercircuit according to an embodiment of the present invention;

FIG. 2 shows a generalised circuit diagram of an embodiment of thepresent invention according to a first realisation of the presentinvention;

FIG. 3 shows a generalised circuit diagram of an embodiment of thepresent invention according to a second realisation of the presentinvention;

FIG. 4 shows a basic embodiment of the present invention according tothe first realisation;

FIG. 5 shows a basic embodiment of the present invention according tothe second realisation;

FIG. 6 shows a first circuit arrangement to provide control voltages toa circuit such as that shown in FIG. 4;

FIG. 7 shows a second circuit arrangement to provide control voltages toa circuit such as that shown in FIG. 4;

FIG. 8 shows a third circuit arrangement to provide control voltages toa circuit such as that shown in FIG. 4;

FIG. 9 shows a fourth circuit arrangement to provide control voltages toa circuit such as that shown in FIG. 4;

FIG. 10 shows a first circuit arrangement to provide control voltages toa circuit such as that shown in FIG. 5;

FIG. 11 shows a second circuit arrangement to provide control voltagesto a circuit such as that shown in FIG. 5;

FIG. 12 shows a third circuit arrangement to provide control voltages toa circuit such as that shown in FIG. 5;

FIG. 13 shows a fourth circuit arrangement to provide control voltagesto a circuit such as that shown in FIG. 5;

FIG. 14 shows a fifth circuit arrangement to provide control voltages toa circuit such as that shown in FIG. 5;

FIG. 15 shows typical variation in collector current under the influenceof increasing RF input power, for various modes, later discussed; and

FIGS. 16 and 17 show results of simulations of a circuit according toFIG. 1, in low power mode and high power mode, respectively.

Features common with those illustrated in other drawings carrycorresponding reference labels.

The maximum available output power from a transistor amplifier is afunction of, amongst other things, the supply current available, forexample shows as collector current Ic in FIG. 1. In an amplifierconfiguration which includes a self biasing mechanism, such that Icincreases with increased RF drive level, then the parameters of the selfbiasing mechanism ultimately limit the maximum output power. In such acase, an “input bias resistance” or bias circuit impedance can beidentified, which limits the available output power that can be achievedat a given linearity. For example, a relatively high input biasresistance tends to lead to a very non-linear amplification, but withexcellent efficiency; whereas a lower input bias resistance will lead tomore linear amplification but with a lesser efficiency. Specifically,for different power and linearity requirements, different biasresistances are required if amplifier efficiency is to be optimised.

According to the present invention, the bias circuit impedance of anamplifier can be adjusted by switching in or out certain resistors of aprovided series resistor chain. In certain embodiments, this switchingfunction is achieved by controlling emitter follower transistors havingvarious associated combinations of resistors.

Although the present invention does not aim to provide a truly variablebias impedance, the present invention does at least provide anapproximation of this function. In particular, circuits suitable for usein mobile telephone handsets are provided, which offer both low and highpower modes of operation. The low power mode is suitable for efficientamplification of signals to a modest power level where linearity must bemaintained, for example with CDMA encoding, or for highly efficientamplification of signals to a high power level, albeit in a verynon-linear manner, as for example may be required with AMPS typeencoding. The high power mode provides efficient amplification ofsignals to a higher power level where linearity must be maintained,again using CDMA encoding for example.

FIG. 1 illustrates a type of amplifier modified according to anembodiment of the present invention. The basic amplifier upon which theembodiment of FIG. 1 is based is described and illustrated in UK patentapplication No. 0304053.2, from which the present application claimspriority, and the corresponding International patent application No.PCT/GB2003/______, filed 18 Mar. 2003. In summary, the amplifieroperates as follows.

In the absence of an RF signal, the control loop 20 operates to providea voltage Vm necessary to set the quiescent current Ic in transistor Tr1to a predetermined value. In this case, the quiescent levels can be set,depending on the voltage at the switch control terminal Vmode. ThisVmode control voltage also operates to simultaneously switch the biascurrent impedance between two corresponding values. These values areeither a low impedance, which may for simplicity be considered to be thesum of the resistances of resistors R23 and R22, or a high impedance,which may for simplicity be considered to be the sum of the resistancesof resistors R24, R23 and R22. The low bias impedance is provided with ahigh quiescent current Ic as a high power mode. The high bias impedanceis provided with a low quiescent current Ic as a low power mode. A moredetailed description of the operation of this circuit will be providedlater.

The present invention relates to the mode control and bias impedancevariation circuitry 40, described in UK patent application No.0304053.2.

As will be further described, and according to an aspect of the presentinvention, a mode signal Vmode may be provided to control the operationof the amplifier, selecting either a high power mode of operation or alow power mode of operation, as described earlier.

In the absence of an input signal RFin, the control loop 20 will fix thequiescent collector current in Tr1 to a certain constant value, whateverthe values of the resistors in the base circuit. When an input signal isapplied, a self-biasing effect may occur. The present invention aims,amongst other things, to compromise between providing only a lowquiescent collector current in Tr1, while still permitting relativelyhigh powered output amplified signals RFout, thus optimising efficiencyfir a given signal linearity requirement.

The present invention is also applicable to other topologies where aself-biasing mechanism is provided, based on a gain element such asemitter follower transistor Tr4, but where the Vm signal is developed byalternative means, such as by monitoring Ic directly, for example. Insuch a case the current mirror transistor Tr2 would not be required, andthe power amplifying transistor Tr1 has its base terminal connectedthrough resistors R21, R22 and R23 to the resistor R24. Resistors R22and R23 may be merged into a single resistor.

Depending on the layout strategy used, large transistor Tr1 may be madeup of N smaller transistors, connected in parallel and each with its ownindependent RF base feed capacitor Cb and DC base feed resistor Rb. TheN transistors, capacitors and resistors are in this case representedlumped together in FIG. 4 as C1=Cb*N and R22=Rb/N.

FIG. 2 shows a generalised form of this first (‘vertical’) realisationof the present invention. A current mirror comprising transistors Tr1and Tr2 is provided, with resistors R20, R21 and R22 in series,connecting their base terminals. A capacitor C1 is connected to the nodebetween resistors R21, R22 and introduces the signal to be amplified. Inan example of an amplifier for a mobile telephone handset, the signalmay be an RF signal for transmission. The DC quiescent point ofoperation of the amplifier is set by the current flowing throughresistors R23, R22 and R21, and circuit operation is further determinedby the state of conduction of the transistors Tr4 a-Tr4 d. Although fourtransistors are shown, more or fewer could be provided, according to thenumber of different bias resistance values it is required to provide.Each of the emitter follower transistors Tr4 a-Tr4 d may be providedwith a base resistor connecting its base terminal to the correspondingnode on the chain of resistors R25; R25 c-R25 a, in order to fine tunethe self-bias profile of the amplifier.

A voltage signal Vm is derived from a signal voltage Vpd and is providedas an input signal by a control circuit symbolically indicated bytransistor Tr7 and diode D1. Such a control circuit may be as shown atreference 20 in FIG. 1, wherein transistor Tr7 and diode D1 may beidentified. For the purposes of the present invention, the entirecircuit 20 may be regarded as a source of a suitable control voltage Vmfor the circuit 40 of the present invention. A current source 26 isprovided, and serves to draw a certain current Im through a chain ofresistors R25; R25 c-R25 a from the voltage signal Vm. Consecutive nodes42, 44, 46, 48 of the resistor chain are each connected to the baseterminal of a respective transistor Tr4 d, Tr4 c, Tr4 b, Tr4 a. Each ofthe emitter follower transistors Tr4 a-Tr4 d may be provided with a baseresistor connecting its base terminal to the corresponding node on thechain of resistors R25; R25 c-R25 a, in order to fine tune the self-biasprofile of the amplifier. Each of these transistors Tr4 d, Tr4 c, Tr4 b,Tr4 a has its collector terminal connected to a supply voltage Vcc, andits emitter terminal connected to a respective node of a further chainof resistors R24; R24 c, R24 b, R24 a. A further resistor R23 connectsthis resistor chain to the node 10 between resistors R20 and R22, thebias current injection point.

The operation of the circuit of FIG. 2 is as follows. Current source 26draws a relatively constant current Im through resistor chain 25,comprising resistors R25 c, R25 b, R25 a. Each of these resistors has anessentially constant resistance. Accordingly, there will be anessentially constant voltage differential between nodes 42 and 44.Another essentially constant voltage differential between nodes 44 and46; and a further essentially constant voltage differential betweennodes 46 and 48. Any variation in the absolute voltage Vm will cause acorresponding absolute variation in the value of the respective voltagesat each node 44, 46, 48. At a relatively high value of Im, the voltageat node 42 may be sufficient to render transistor Tr4 d conductive, butthe voltages at nodes 44, 46 and 48 may respectively be insufficient torender transistors Tr4 c, Tr4 b and Tr4 a conductive. The bias impedanceof Tr1 will accordingly include all of resistors R21, R22, R23, R24 a,R24 b and R25 c. At a lower value of Im, the voltages at nodes 42 and 44may both be sufficient to render both associated transistors Tr4 d andTr4 c conductive. The voltages at nodes 46 and 48 may still beinsufficient to render their respective transistors Tr4 b, Tr4 aconductive. Accordingly, the bias impedance for transistor Tr1 includesresistors R21, R22, R23 R24 a and R24 b but not resistor R24 c.Similarly, at a relatively low value of current Im, all of nodes 42, 44,46 and 48 may be at voltages high enough to render their respectiveassociated transistors Tr4 d-Tr4 a conductive. In this case, the biasimpedance for transistor Tr1 includes resistors R21, R22 and R23, butnot resistors R24 a, R24 b, R24 c.

Other numbers of transistors Tr4 and resistors R25, R24 may be provided,and the operation will be analogous. Other methods and apparatus may beprovided for selectively rendering transistors Tr4 a-Tr4 d conductive.Some of these alternatives will be discussed below.

FIG. 3 shows a generalised form of an alternative (‘horizontal’)realisation of the present invention. The current mirror comprisingtransistors Tr1 and Tr2 is again provided, although the presentinvention is also applicable to amplifiers which do not include thecurrent mirror transistor Tr2. In such case, the power amplifyingtransistor Tr1 has its base terminal connected through resistors R21,R22 to the resistor chain R24 a′-R24 c′.

Resistors R20, R21 and R22 are again placed in series between therespective base terminals of transistors Tr1 and Tr2. However, in thisalternative realisation, the resistor chain referred to as R24 c-R24 ain the vertical realisation of FIG. 2 is replaced by a ‘horizontal’resistor chain R24 c′-R24 a′ placed in series between resistors R20 andR22. Respective transistors Tr4 d′, Tr4 c′, Tr4 b′, Tr4 a′,corresponding to transistors Tr4 d-Tr4 a of the realisation of FIG. 2,have their respective emitter terminals connected to respective nodesbetween resistors of the resistor chain R20, R24 c′-R24 a′, R22. Thetransistors Tr4 d′ each have their base terminal connected to respectivenodes 42, 44, 46, 48 of the resistor chain R25 c-R25 a, as describedwith reference to FIG. 2. Each of the emitter follower transistors Tr4a′-Tr4 d′ may be provided with a base resistor connecting its baseterminal to the corresponding node on the chain of resistors R25; R25c-R25 a, in order to fine tune the self-bias profile of the amplifier.The remainder of the circuit is as described with reference to FIG. 2.In the example of an amplifier for a mobile telephone handset, thesignal RFin may be an RF signal for transmission. The DC quiescent pointof operation of the amplifier is set by the DC current flowing throughresistors R22 and R21, and circuit operation is further determined bythe state of conduction of the transistors Tr4 a′-Tr4 d′.

The operation of the circuit of FIG. 3 is as follows. Current source 26draws a relatively constant current In through resistor chain 25′,comprising resistors R25 c, R25 b, R25 a. Each of these resistors has anessentially constant resistance. Accordingly, there will be anessentially constant voltage differential between nodes 42 and 44.Another essentially constant voltage differential between nodes 44 and46; and a further essentially constant voltage differential betweennodes 46 and 48. Any variation in the absolute voltage Vm supplied bycontrol circuit 20 will cause a corresponding absolute variation in thevalue of the respective voltages at each node 44, 46, 48. At arelatively high value of Im, the voltage at node 42 may be sufficient torender transistor Tr4 d′ conductive, but the voltages at nodes 44, 46and 48 may respectively be insufficient to render transistors Tr4 c′,Tr4 b′ and Tr4 a′ conductive. The bias impedance of Tr1 will accordinglyinclude all of resistors R21, R22, R24 a′, R24 b′ and R25 c′. At a lowervalue of Im, the voltages at nodes 42 and 44 may both be sufficient torender both associated transistors Tr4 d′ and Tr4 c′ conductive. Thevoltages at nodes 46 and 48 may still be insufficient to render theirrespective transistors Tr4 b′, Tr4 a′ conductive. Accordingly, the biasimpedance for transistor Tr1 includes resistors R21, R22, R24 a′ and R24b′ but not resistor R24 c′. Similarly, at a relatively low value ofcurrent Im, all of nodes 42, 44, 46 and 48 may be at voltages highenough to render their respective associated transistors Tr4 d′-Tr4 a′conductive. In this case, the bias impedance for transistor Tr1 includesresistors R21 and R22, but not resistors R24 a′, R24 b′, R24 c′. Thiswould be used for a high power/high quiescent current mode.

Other numbers of transistors Tr4′ and resistors R25, R24′ may beprovided, and the operation will be analogous. Other methods andapparatus may be provided for selectively rendering transistors Tr4a′-Tr4 d′ conductive. Some of these alternatives will be discussedbelow.

Semi-lumped power cell build refers to a technique of physical layout onchip, whereby large transistor Tr1 may be built up of N smallertransistors, where individual or small groups of these smallertransistors are DC fed from a common node (in this case, the nodebetween R21 and R22) through a single or a small bank of low valuedresistors. These resistors are collectively represented as R21 in FIG.3. An input signal, such as an RF signal, is injected into this commonnode through a single capacitor C1. Resistor R22 sets the minimum biasimpedance that can be achieved.

The horizontal realisation has certain advantages. In both high and lowpower modes, the current flowing in the Tr2 collector remain moreconstant than in the equivalent ‘vertical’ realisation when differentemitter followers Tr4* are activated, due to the changing bias injectionpoint altering the DC mirror function between the two transistors Tr1and Tr2. Keeping the collector current in Tr2 more constant in differentmodes helps the operation of the control loop, and is a possiblealternative to needing to modify the ‘reference’ or ‘sense’ outputs ofthe circuit 20.

On the other hand, the horizontal realisation does have a disadvantage,in that the changing bias injection point causes the base feed resistorsof transistors Tr1 and Rr2 to be no longer in exact proportion to thetransistor areas, making the circuit more prone to unwanted asymmetriccurrents forming over temperature, and possible thermal runaway of Tr1.

FIG. 4 shows a simple embodiment of the present invention according tothe first (‘vertical’) realisation. Two emitter followers Tr4 a, Tr4 bare provided. The emitter followers are selectively enabled byappropriate application of voltages Vcc, Vb_EF1 and Vb_EF2. Examples ofthe arrangement of these voltages will be discussed below. When emitterfollower Tr4 b is activated by a relatively high voltage on Vb_EF2,quiescent current is supplied to transistors Tr1 and Tr2 through a biasimpedance including both resistors R24 a and R23. Such bias arrangementwould be particularly suited to operation in a low power/low quiescentcurrent mode. When the emitter follower Tr4 a is activated by arelatively high voltage on Vb_EF1, quiescent current is supplied totransistors Tr1 and Tr2 through a bias impedance including resistor R23but not resistor R24 a. Such bias arrangement would be particularlysuited to operation in a high power/high quiescent current mode.

Resistors R20 and R22 have values in the ratio N:1, where N representsthe ratio of the emitter areas of the transistors Tr1, Tr2, transistorTr1 has an emitter area N times the emitter area of Tr2. Resistor R21 isset to zero. The capacitance of capacitor C1 is selected to be Cb*N,where Cb is the base input capacitance of the transistor Tr1. Only tworesistors are provided in the resistor chain 24, being resistors R23 andR24 a. Correspondingly, only two controlled emitter followers Tr4 a andTr4 b are provided. The base terminals of the transistors Tr4 a and Tr4b are connected to respective control signals Vb_EF1 and Vb_EF2.

FIG. 5 illustrates a first particular embodiment of the presentinvention according to the second (‘horizontal’) general realisation ofthe present invention. Transistor Tr1 has an emitter area N times theemitter area of Tr2. Only four resistors are provided in the resistorchain 24′, being resistors R20, R24 a′, R22 and R21. Correspondingly,only two controlled emitter followers Tr4 a′ and Tr4 b′ are provided.The base terminals of the transistors Tr4 a′ and Tr4 b′ are connected torespective control signals Vb_EF1 and Vb_EF2.

Different quiescent bias points require different bias impedances for agiven modulation type. Higher RF input levels require lower biasimpedances and higher quiescent points, to avoid distortion of theamplified signal, where linearity is important. The circuit of FIG. 5,and other circuits discussed in the present application, aim to providea bias impedance that is a function of an input signal level.

Circuitry (not illustrated) is connected to the circuitry of FIG. 5 toprovide a base voltage Vb_EF1 to transistor Tr4 a′ which is lower thanthe base voltage Vb_EF2 applied to transistor Tr4 b′. This circuitry maybe as illustrated in FIGS. 2 and 3, or may be any other suitablecircuitry. In a given ‘low power’ condition, transistor Tr4 b′ isconductive but transistor Tr4 a′ is not conductive, due to its lowerapplied base voltage. All of the base drive current to transistor Tr1 issupplied through transistor Tr4 b′ and resistors R24 a′, R22 and R21.Operation will settle at a certain level of quiescent current, in theabsence of any input signal RFin.

In the absence of an input signal RFin, or where the input signal is ata low level, the circuit will operate in a ‘low power’ mode. The biasimpedance of transistor Tr1 will be relatively high, as resistor R24 a′is included. The current ratio between transistors Tr2 and Tr1 willapproximate to R20: (R24 a′+R22+R21). This would be used for a lowpower, low quiescent current mode.

With a high level of input signal RFin, but with transistor Tr4 a′ stillnon-conductive, the voltage perturbations at the emitter of transistorTr4 a′ are of adequate magnitude to cause transistor Tr4 a′ to operateas an emitter follower, at least on the negative-going half cycles ofthe voltage perturbations. The circuit will begin to operate in a ‘highpower’ mode. The bias impedance to transistor Tr1 will be low, asresistor R24 a′ will be excluded from the bias resistance of transistorTr1, at least for the negative-going half cycles of the perturbations.The base current ratio between the transistors approximates to (R20+R24a′): (R22+R21).

At input signal levels between these extremes, an intermediate biasimpedance and current ratio will be provided. Further emitter followersand resistors may be added, as discussed with reference to FIG. 3, inorder to smooth the transition between ‘high’ and ‘low’ power modes, andto thereby maintain linearity over a large power range.

It can accordingly be seen that the bias injection point effectivelychanges as a function of the input signal RFin level. This in turnaffects the base current ratios between Tr1 and Tr2, such that thecurrent in Tr2 varies significantly less than the current in transistorTr1. By suitably selecting the component values, it may be possible toachieve all of the required bias impedance variation without changingany of the applied voltages Vcc, Vb_EF1 and Vb_EF, such that the levelof the incoming signal RFin determines the bias injection point withoutthe intervention of other circuitry. Weighing against this option is thepossibility of thermal runaway. To avoid the possibility of thermalrunaway, the ‘vertical’ arrangement of FIG. 2 may be used, providinginput signal level controlled variation of the bias impedance in asimilar way, although the quiescent current level would need to beadjusted independently, according to the level of the input signal RFin.For example, a rectified copy of the input signal could be used tocontrol the quiescent current level.

Further particular embodiments of the circuits discussed with referenceto FIGS. 2-5 will be discussed in the following part of the description.

FIG. 6 shows a particular embodiment of the circuit of FIG. 4. Here, amode control voltage Vmode is provided, to enable only a selected one oftransistors Tr4 a or Tr4 b. This is achieved by causing voltage Vmode toapply inverse control voltages to respective switches 61, 62, eachcapable of connecting and disconnecting a respective collector terminalof transistors Tr4 b, Tr4 a to/from the supply voltage Vcc. Theremainder of the circuit is as described with reference to FIG. 4.Obviously, resistor R24 a may only form a component of the baseimpedance of transistor Tr1 when transistor Tr4 b is enabled by theclosure of switch 61. Resistor R23, on the other hand, may form acomponent of the base impedance of the transistor Tr1 whichever of thetransistors Tr4 a, Tr4 b are enabled. Switches 61 may be embodied asmechanical relays, transistors or other semiconductor devices asrequired. These switches may need to be realised off-chip. Care must betaken to avoid excessive base-emitter leakage through the non-enabledemitter follower transmitter Tr4*, particularly if operated at high RFpower.

In FIG. 7, the Vmode signal is not used to control transistors Tr4 a,Tr4 b. The collector terminals of these transistors are connected tosupply voltage Vcc. Rather, separate base control signals Vpd2, Vpd1 areprovided to the respective base terminals of transistors Tr4 b, Tr4 a.An additional, controlled signal Vpd must accordingly be provided. Thisproblem may be avoided as described below with reference to furtherembodiments. The remainder of the circuit is as described with referenceto FIG. 4.

The embodiment of FIG. 8 represents, to a certain extent, a combinationof the embodiments of FIGS. 6 and 7. The Vmode signal enables only aselected one of the transistors Tr4 a, Tr4 b. The collector terminal ofeach transistor Tr4 a, Tr4 b are connected directly to the supplyvoltage Vcc. The Vmode signal operates, in this embodiment, to enable ordisable the provision of a single base signal Vpd to the respective baseterminals of the transistors Tr4 a, Tr4 b. This is achieved by applyinga pull-down voltage to one of the base input paths of transistors Tr4 aand Tr4 b. Resistors 81, 82 are placed in series between a base terminalof transistor Tr4 b and the control voltage Vpd. Resistors 83, 84 areplaced in series between a base terminal of transistor Tr4 a and thecontrol voltage Vpd. The respective node between each of these pairs ofresistors is connected by way of a respective third resistor 85, 86, tothe collector of a respective pull-down transistor 87, 88. Pull-downtransistor 88 is controlled by voltage Vmode at its base terminal,through base resistor 89. Pull-down transistor 87 is controlled throughbase resistor 90 by the collector voltage of pull-down transistor 88.This collector voltage represents the inverse of voltage Vmode. Hence,when Vmode is at a high value, transistor 88 is conductive, itscollector voltage is low and the base voltage of transistor Tr4 a ispulled low. Transistor Tr4 a is accordingly held in a non-conductivestate. At the same time, the base voltage of transistor 87 is low.Transistor 87 is non-conductive and the base voltage of transistor Tr4 bis as determined by signal Vpd. Transistor Tr4 b becomes conductive asdetermined by signal Vpd, and resistors R23 and R24 a each formcomponents of the base impedance of transistor Tr1.

Conversely, when Vmode is at a low value, transistor 88 isnon-conductive, its collector voltage is determined by the signal Vpdand transistor Tr4 a is rendered conductive as determined by appliedvoltage Vpd. At the same time, the base voltage of transistor 87 ishigh, according to the value of Vpd. Transistor 87 is accordinglyrendered conductive, pulling the base terminal of transistor Tr4 b low.Transistor Tr4 b is held non-conductive, allowing resistor R23, but notresistor R24 a, to form components of the base impedance of transistorTr1.

The circuit arrangement of FIG. 8 has advantages in that it can be fullyintegrated in an on-chip solution; no off-chip components are required.It is simple to expand the circuit solution of FIG. 8 to include moreemitter followers Tr4* than the two shown. However, the circuit of FIG.8 does have some drawbacks. The current Ipd drawn from the signalvoltage Vpd is increased due to the current required to pull down theunused emitter follower transistor's base voltage. The circuit providesan effective low power mode suitable for CDMA encoding in mobiletelephone handsets, but may not provide a sufficiently powerful highpower mode for operating AMPS encoding.

FIG. 9 shows a further variant of the circuit of FIG. 8. In thisembodiment, the base terminal of transistor Tr4 b is connected to signalVpd through resistors 82, 81. The base terminal of transistor Tr4 a isconnected through resistor 84 to the node 95 between resistors 81 and82, which is at a voltage Vx. The voltage at the base terminal oftransistor Tr4 a is at a voltage indicated as Vz. While transistor Tr4 bis effectively always controlled by signal Vpd through resistors 81 and82, transistor Tr4 a is enabled or disabled by signal Vmode as follows.Signal Vmode is applied through resistor 89 to the base of transistor88, as in FIG. 8. The collector of transistor 88 is connected throughresistor R100 to the emitter of a further transistor Tr100. The baseterminal of transistor Tr100 receives the controlling voltage Vpd, whilethe collector of transistor Tr100 is connected to the base terminal oftransistor Tr4 a.

When Vmode is at a high level such as 3.0V, transistor 88 is renderedconductive. This draws a current from resistor R100, and pulls thevoltage at the emitter terminal of transistor Tr100 to less than one Vbebelow Vpd, turning transistor Tr100 on. Transistor Tr100 then operatesas a DC current source, drawing a constant current through resistor 84.This in turn brings the voltage Vz at the base terminal of transistorTr4 a to a lower value, turning transistor Tr4 a off. Transistor Tr4 bis conductive, as determined by signal voltage Vpd. Resistors R24 a andR23 both form components of the base impedance for transistor Tr1. Allthe bias current to transistors Tr1 and Tr2 flows in transistor Tr4 b,through resistors R24 a and R23. The circuit operates as required for alow quiescent current, low power and high bias impedance mode, suitablefor low power CDMA.

When Vmode is at a low level such as 0V, transistor 88 is renderednon-conductive. No current is drawn from resistor R100, and thebase-emitter voltage of transistor Tr100 remains less than Vbe, causingtransistor Tr100 to remain non-conductive. This in turn leaves thevoltage Vz at the base terminal of transistor Tr4 a unaffected.Transistor Tr4 a may be rendered conductive, according to signal voltageVpd. Transistor Tr4 b is conductive, as determined by signal voltageVpd. Resistors R24 a and R23 both form components of the base impedancefor transistor Tr1. However, the path through transistor Tr4 a willdominate, due to the presence of the resistance R24 a, and the overalleffect will be virtually the same as simply admitting resistor R23 intothe base impedance of transistor Tr1. The circuit accordingly runs inhigh bias current/high power mode, suitable for high power CDMA.

Both modes support saturated modulated signals such as AMPS as well. Thehigh power mode allows a high input signal (RF) power to be reached withmodest efficiency, but the circuit is designed so that it is better torun AMPS in the low power mode. Here, the low power efficiency is higherdue to the lower quiescent current. As the power increases, there comesa point where the voltage swing at the emitter follower nodes issufficiently great that the emitter follower Tr4 a becomes active again,and high power can be achieved, albeit in a somewhat more non-linearfashion.

Advantages provided by the circuit of FIG. 9 include effective switchingbetween high and low current modes, controlled by the Vmode signal; itis simple to expand the circuit of FIG. 9 to control more than the twoemitter followers Tr4* shown in the diagram; both low power mode and aneffective high power mode capable of supporting high power AMPS may beobtained. The circuit may be realised fully on-chip. No off-chipcomponents are required. A potential drawback of the circuit of FIG. 9is in that a certain increase in Ipd is required to pull the unusedtransistor's base voltage down.

While the arrangements of FIGS. 6-9 have been discussed in the contextof the first (‘vertical’) general realisation as shown in FIG. 2,corresponding arrangements may be applied in the context of the second(‘horizontal’) general realisation of FIG. 3.

FIGS. 10-14 show certain particular arrangements according toembodiments of the present invention, according to the second(‘horizontal’) general realisation as shown in FIG. 3. These circuitoptions aim to provide a bias impedance for transistor Tr1 which is afunction of the level of the input signal RFin. The circuits shownprovide ‘quasi-variable’ bias impedance, in lieu of a truly linearlyvarying bias impedance. There is some risk of thermal runaway in suchhorizontal arrangement, but other advantages of this arrangement mayoutweigh any such difficulty.

FIG. 10 shows a variant of the circuit of FIG. 5, in which therespective base terminals of the transistors Tr4 a′, Tr4 b′ are providedby signal Vpd through respective different series resistors 121, 122;123, 124. A current of value Ie is drawn from the combination of diodes111, 112 by the control loop 20. This will cause differing voltages atnodes 125, 126 respectively lying between resistors 121 and 122; andresistors 123 and 124. These differing voltages will have respectivediffering effects on the states of conduction of the transistors Tr4 a′,Tr4 b′. The ratios of the values of resistors 123 and 113; and 121 and114 in combination with the other components are contrived such that,for a given value of Ie, the base voltage of transistor Tr4 a′ will belower than the base voltage of transistor Tr4 b′.

Advantages of the circuit arrangement of FIG. 10 include its simplicity,and the ease with which the circuit may easily be expanded to supplymore than the two emitter follower transistors Tr4* shown. However, theabsolute difference between the base voltages of the emitter followertransistors Tr4* will be variable as Ie varies, for example in order tomaintain the value of Ic with temperature, and the high values ofresistors required may compromise the RF performance of the circuit.

FIG. 11 shows a variation on the circuit of FIG. 10, and represents analternative bias arrangement which also allows the bias impedance totransistor Tr1 to vary with the level of the input signal RFin. In theembodiment of FIG. 12, the signal voltage Vpd is applied to a resistorchain 131, 132, 133, which in turn feeds a diode 128 to supply currentIe to control loop 20. Since current Ie causes a voltage drop acrossresistor 132, the voltage at node 125, supplied through resistor 122 tothe base terminal of transistor Tr4 a′ will be less than the voltage atnode 126, provided through resistor 124 to the base terminal oftransistor Tr4 b′, by a value equal to the product of Ie and theresistance of resistor 132.

The arrangement shown in FIG. 11 is also simple, and can be simplyamended to provide base voltages for more than the two emitter followertransistors Tr4* shown. However, as with the circuit of FIG. 10, theabsolute difference between the base voltages of the emitter followertransistors Tr4* will be variable as Ie varies, for example in order tomaintain the value of Ic with temperature, and the high values ofresistors required may compromise the RF performance of the circuit.

FIG. 12 shows a variation on the circuit of FIG. 11. Resistor 132 iseffectively set to zero, placing both nodes 126, 125 at a same voltage,Vx. The control loop 20 sets up a certain current Ie, which in turnestablishes a certain voltage at Vx. Circuitry 135-139 represents acurrent mirror driven by signal voltage Vpd. This current mirror drawsadditional current Ipull through resistor 139, effectively loweringvoltage Vy at the node between resistors 122 and 139, thereby loweringthe base voltage of transistor Tr4 a′, in response to a high value ofcontrol voltage Vpd. The difference between voltages Vx and Vy, andaccordingly between the base voltages of the transistors Tr4 b′ and Tr4a′ is approximately constant.

The arrangement shown in FIG. 12 can be simply amended to provide basevoltages for more than the two emitter follower transistors Tr4* shown.However, the values of resistors required may compromise the RFperformance of the circuit.

FIG. 13 shows a development of the circuits of FIGS. 10 and 12. Thecontrol loop 20 is modified such that the output transistor Tr7 isreplaced with two identical transistors 141, 142 transistors inparallel, and sets up a certain current Ie through resistors 121, 113and diode 111. This current in turn establishes a certain voltage at Vx.A current mirror 141, 142 causes an identical current Ie to be drainedfrom diode 112. A further current mirror 143, 144, controlled by signalvoltage Vpd, draws a further current Ipull from diode 112. The value ofIpull is set by voltage signal Vpd and the value of resistor 145. Thecombined current of (Ie+Ipull) causes a corresponding drop in thevoltage Vy. When Vpd=0, causing Ipull=0, then Vx=Vy. When Vpd>Vbe,causing Ipull>0, Vy<Vx. For the circuit shown, Ipull will be virtuallyconstant, leading to a similarly virtually constant difference betweenVx and Vy.

FIG. 14 illustrates the embodiment of FIG. 9 adapted for use in arealisation according to the second general realisation of FIG. 3. Thesignal Vmode may be connected to the control loop 20 if required. Thisfigure also serves as an illustration of how the various embodimentsdescribed above with reference to one or other of the generalrealisations of FIGS. 2-3 may be adapted for use in an embodimentaccording to the respective other realisation.

The transistor switch 88 pulls the resistor R100 to the ground voltagewhen a high Vmode signal is applied. The signal voltage Vpd is appliedto the base of transistor Tr100, and causes the collector connection ofTr100 to operate as a DC current source, due to the presence of resistorR100. The current drawn by this current source reduces the voltage atVz, causing the base voltage of transistor Tr4 a′ to be at a lower valuethan the base voltage of transistor Tr4 b′, due to the voltage dropacross resistor 84 caused by the current drawn by transistor Tr100.

Under low level input signal RFin, transistor Tr4 a′ will benon-conductive as its base voltage is lower than that of Tr4 b∝0. Thecircuit is arranged such that transistor Tr4 b′ is conductive, and thetransistor Tr1 is biased through transistor Tr4 b′ and resistors R24 a′,R22 and R21. As the input signal level is increased, the voltage at thebases of transistors Tr1 and Tr2 vary. At least on the negative-goinghalf cycles, the base-emitter voltage of transistor Tr4 a′ may becomesufficient to bring that transistor into conduction, thereby reducingthe bias impedance to Tr1. This circuit has the advantages of beingrelatively simple, and easy to expand to control more than the twoemitter follower transistors Tr4* shown, which in turn may provide asmoother more linear variation in bias impedance.

A more complete description of the operation of the circuit of FIG. 1will now be provided. The circuit of FIG. 1 represents an example poweramplifier schematic for a practical circuit that provides the following:a high power mode for CDMA; a low power mode for CDMA; and AMPScompatible in both high power and low power modes.

Typical values for Vcc are 3.0V-6.0V, and Vpd is typically 2.8V. Foroperation in high power mode, the control signal Vmode is set low, forexample at 0V. Transistor Tr12 is off. Tr10 and Tr11 are also off, andeffectively not in circuit. The control loop 20 works largely asdescribed in UK Patent Application GB0304053.2 and sets the Tr1collector current to the desired level. The configuration of thecircuit, by the removal of the C2 capacitor, and the splitting of Tr4into two separate transistors, and the inclusion of extra resistorsR20-R25 gives the circuit a self-biasing mechanism suitable for poweramplifiers as described above. Preferably, the ratio of resistor valuesR20:(R22+R21) is set to be the same ratio as Tr2 emitter area: Tr1emitter area. With no input signal RFin applied, the bias currentinjected into Tr1 and Tr2 will be in the ratio of the device areas, andwill be largely supplied by Tr4 a. Tr4 b will be largely deactivated,since the relatively large value of R24 will make Tr4 a the preferredroute for the bias current. Under increasing input signal drive level,the ‘forward’ current half cycle will itself drive the base of Tr1through C1. During this half of the input signals cycle, the voltage atemitter of Tr4 a will be slightly higher, increasingly deactivating it.During the ‘reverse’ current half cycle, the input signal current flowin the opposites direction through C1 will come largely from the Tr4 aemitter, through a bias impedance of approximately R23+R22. The net DCcurrent into Tr1 increases, and the circuit effectively self biases to ahigher level to support the amplified output signal RFout level requiredin an efficient manner. A linear (e.g. CDMA) or saturated (e.g. AMPS)signal can be used in this mode. For the AMPS signal it will be moreusual to use the low power mode.

For operation in the low power mode, the control signal Vmode is set toa relatively high value, such as 3.0V. With Vmode high, transistor Tr12is on. Tr10 and Tr11 are therefore also on. The Vpd feed to the bases ofthese devices in combination with the emitter resistors to ground causethe collectors of Tr10 and Tr11 to operate as good DC current sources.The DC current flowing in Tr10 adds to the current flow in R4. Thecurrent flow in R4 is used by the control loop 20 to ‘measure’ thecurrent in Tr1. This extra current in R4 will cause the control loop 20to react as if transistor Tr1 were running at a higher collector currentlevel than required. The bias circuit control loop 20 will thereforecompensate to make the current flowing in R4 equal to that flowing in R3as usual. In this way, Tr1 collector current will be reduced to a leveldesired for low power mode operation. The Tr11 current sourceeffectively places a negative voltage offset on the base of Tr4 a withrespect to the base of Tr4 b by the action of it passing through R25.This effectively deactivates Tr4 a. Transistors Tr1, Tr2 are thereforebiased by current flow from the emitter of Tr4 b. Under low, butincreasing input signal drive level, the ‘forward’ current half cyclewill drive the bases of transistors Tr1 and Tr2 through C1. During thishalf of the input signal cycle, the voltage at emitter of Tr4 b will beslightly higher, increasingly deactivating it. During the ‘reverse’current half cycle, the input signal current flow in the oppositedirection through C1 will come largely from the Tr4 b emitter, through abias impedance of approximately R24+R23+R22, a higher bias impedance asrequired for low power mode of operation. This allows for a moreefficient CDMA amplification, but up to a lower maximum output power. Ifa higher output power is required, the circuit needs to be switched intothe high power state.

For AMPS signals on the other hand, the low power mode offers efficientAMPS amplification for low level signals, but also for high levelsignals, due to an additional mechanism that comes into play. As inputsignal levels increase further, there comes a point where the inputsignal voltage swing at the base nodes of Tr1 and Tr2 reachessufficiently high level to overcome the base offset voltage (Im.R25) ofTr4 a, and this transistor becomes active again. Under these conditionsthe bias impedance drops to approximately the value in the high powermode, and an AMPS signal continues to be amplified to a very high powerlevel. In this two-transistor implementation for Tr4, this mechanism isnot suitable for CDMA due to the negative impact on linearity.Additional Tr4 elements can be added to improve the linearity to higherlevels, and ultimately it is possible that several sections could beused to provide a scheme that allows a high power CDMA signal to bedeveloped from a very low starting quiescent bias point. This approachwould allow for a very efficient and simple power amplifier to berealised.

FIG. 15 shows the relationship between the input power Pin, being theinput signal power supplied by RFin, and Ic, the collector current oftransistor Tr1 which in turn is proportional to Pout, being the outputpower as supplied by RFout. The relationship typically follows anon-linear relationship as shown by each of the curves 161, 162, 163 and170.

Curve 161 shows the typical input/output power relationship for anamplifier according to the present invention operating in high biasresistance and low power, low quiescent power mode. Curve 170 shows thecorresponding curve for the amplifier operating in low bias resistanceand high power, high quiescent current mode. As is clear from FIG. 15,the output power Pout is much greater when the amplifier operates in lowbias resistance mode as compared to when it operates in high biasresistance mode, for a given value of input power Pin.

The offset value, being the value of Ic when Pin=0 is the quiescentcollector current in transistor Tr1. This is controlled by the value ofthe applied voltage Vpd or Vm, according to the various embodiments ofthe invention described above. By setting a higher quiescent current intransistor Tr1, a higher output power can be achieved, at the expense ofa shorter battery life between recharging steps. Considering the curves161, 162 and 163, it is apparent that the gradient of the curve, andhence the amplification for any given input signal power Pout may bevaried while retaining a same offset. This may be achieved by varyingthe current drawn by the current source 26 of FIGS. 2 and 5, by anysuitable means. This variation will, of course, affect the absolutepotential difference between the base voltages of the emitter followertransistors Tr4*, in turn altering their level of sensitivity toincreased input signal power Pin.

FIGS. 16 and 17 show results of simulations of a circuit according toFIG. 1, in low power mode and high power mode, respectively.

FIG. 16 represents various features of the circuit as functions of inputpower (Pin), when the circuit of FIG. 1 is operated in low power mode,with the Vmode signal set to 3.0V. Curve 161 is scaled against theleft-hand y-axis, and shows output power from the amplifier of FIG. 1.Traces 162 and 163 show adjacent channel power traces for the 1st and2nd adjacent channels, respectively, scaled against the left-handy-axis. These parameters indicate how linear the amplifier is. The morenegative the number the better.

Curve 164 shows collector current of transistor Tr1, scaled against theright-hand y-axis. Curve 165 is also scaled against the right-handy-axis, and shows efficiency normalised to a number 0-1 (i.e. 0-100%).

FIG. 17 shows corresponding curves for the amplifier operated in highpower mode with the Vmode signal at 0V.

A significant difference is the first adjacent channel 162 green traceis maintained at a lower level (more linear), up to the point that theoutput power 161 starts to saturate. This improved linearity is achieveddue to the circuit operating with a lower bias resistance, and higherquiescent current of around 100 mA, compared to 30 mA in the low powermode. The quiescent current being the flat portion of the Ic (164)curve. Whilst better linearity can be achieved at high power levels, theefficiency of this mode is not so good at low power levels—thisdemonstrating an advantage of the dual mode of operation on long termbattery efficiency.

According to a certain aspect of the present invention, these isprovided a bias circuit that changes mode under the influence of RFsignal level and/or a control signal (Vmode). These modes may involvechanging bias circuit impedances and/or quiescent currents, allowingdifferent tradeoffs between output power, linearity and efficiency to berealised. Certain embodiments of the invention aim to provide a biasimpedance that is a function of an input signal level.

While the present invention has been described with reference to alimited number of particular embodiments, many modifications may be madewithin the scope of the present invention. For example, although variousbias circuits have been illustrated and described, any suitable biascircuit could be used which achieves the required effect. While thepresent invention has been described with exclusive reference to npntransistors, the invention may be transposed for use with pnptransistors, or a mixture of pnp and npn transistors, with appropriatereversal of voltage polarities. The present invention may also beembodied in other types of circuit device, such as JFETs or MOSFETS.

1. A method for optimizing power consumption in a transistor amplifier,comprising the step of adapting the amplifier characteristics of thetransistor (Tr1) by adapting the bias impedance at the base of thetransistor, characterized in that this step comprises the sub-steps of:providing a bias resistor chain comprising at least one resistor betweenthe base of the transistor (Tr1) and a bias supply voltage; providing atleast one emitter follower transistor (Tr4*) having its emitterconnected to a node of the bias resistor chain and receiving a controlvoltage at its base; connecting the base of the transistor (Tr1) to thebias supply voltage through at least one of the emitter followertransistor(s) in response to a respective control voltage applied to theor each base of the emitter follower transistor(s).
 2. The methodaccording to claim 1, further comprising the step of adapting theamplifier characteristics of the transistor (Tr1) by adapting thequiescent collector current in the transistor (Tr1).
 3. A methodaccording to claim 2 wherein the quiescent collector current iscontrolled by a control loop, wherein the collector current is mirroredby a current mirror and controlled by reference to the current in thecurrent mirror, and wherein the step of adapting the quiescent collectorcurrent in the transistor (Tr1) comprises artificially adjusting theapparent current flowing in the current mirror, thereby causing thecontrol loop to adjust the collector current in the transistor (Tr1) inaccordance with the adjusted apparent current flowing in the currentmirror.
 4. A method according to claim 3 wherein a mode signal isprovided, and the apparent current flowing in the current mirror (Tr2)is adjusted in response to the mode signal.
 5. A method according to anypreceding claim wherein a mode signal is provided, and the respectivecontrol voltage(s) is/are adjusted in response to the mode signal.
 6. Amethod according to claim 1, wherein the bias resistor chain comprisesat least two resistors, a first of said resistors being placed betweenthe base of the transistor (Tr1) and the emitter of the associated,first, emitter follower transistor (Tr4 a, Tr4 a′), the second of saidresistors being placed between the emitter of the first emitter followerand the emitter of an associated, second, emitter follower (Tr4 b, Tr4b′), the base of the first emitter follower transistor being arranged toreceive a bias voltage lower than a bias voltage supplied to the base ofthe second emitter follower.
 7. A method according to claim 1, furthercomprising the step of AC coupling a signal to be amplified to the baseof the transistor (Tr1), whereby the signal to be amplified causesvariations in the conductive state of at least one of the emitterfollowers.
 8. An amplifier arranged for optimized power consumption,comprising a transistor (Tr1), a source of signal to be amplified, andbias circuitry, characterized in that the bias circuitry comprises:circuitry for adapting the bias impedance at the base of the transistor(Tr1), such circuitry itself comprising: a bias resistor chaincomprising at least one resistor connected between the base of thetransistor (Tr1) and a bias supply voltage; at least one emitterfollower transistor (Tr4*), each having its emitter connected to a nodeof the bias resistor chain and each connected to receive a respectivecontrol voltage at its base; wherein the emitter follower transistorsare connected so as to adjust the bias impedance at the base of thetransistor (Tr1) by adjusting their conductivity in response to therespective control voltage.
 9. An amplifier according to claim 8,further comprising means for adapting the quiescent collector current inthe transistor (Tr1).
 10. An amplifier according to claim 9 wherein themeans for adapting the quiescent collector current comprises a currentmirror arranged to mirror the collector current in the transistor (Tr1),and a control loop responsive to the current in the current mirror toadapt the collector current in accordance with the current in thecurrent mirror.
 11. An amplifier according to claim 10 furthercomprising means (Tr10) for artificially adjusting an apparent currentflowing in the current mirror, and wherein the control loop is arrangedto adjust the collector current in the transistor (Tr1) in accordancewith the adjusted apparent current flowing in the current mirror.
 12. Anamplifier according to claim 11 wherein a mode signal is provided, andis arranged to artificially adjust the apparent current flowing in thecurrent mirror.
 13. An amplifier according to claim 1, wherein a modesignal is provided, and the respective control voltage(s) is/arearranged to vary in response to the mode signal.
 14. An amplifieraccording to claim 1, further comprising an AC coupling arranged tosupply a signal to be amplified to the base of the transistor (Tr1), theat least one emitter follower being arranged such that the signal to beamplified causes variations in the conductive state of the at least oneemitter follower.
 15. A method or an amplifier according to claim 3,wherein the resistor chain is connected between the base of thetransistor (Tr1) and a base of the current mirror. 16-17. (canceled) 18.An amplifier according to claim 10, wherein the resistor chain isconnected between the base of the transistor (Tr1) and a base of thecurrent mirror.